Digital processors operate generally synchronous to a processing clock by sequentially execution instructions that are stored in a program memory. However, such processors have to interface with external devices. One means of interfacing is performed by a so-called interrupt. Such an event interrupts the sequential execution of a program and forces the processor to enter into an exception state in which the processor executes a so-called interrupt service routine. During this service routine the external event is processed. Contrary to the synchronous execution of a ‘normal’ program an interrupt signal generally occurs asynchronously. In other words, such an external signal may occur at any time during the execution of a currently processed instruction. Such an interrupt is generally acknowledged in the following cycle. To pre-process the interrupt, depending on implementation, the currently pending instruction or even the next following instruction is generally executed before the processor is interrupted. The time from the occurrence of an external interrupt to the time at which the service routine is actually executed is called latency. This latency depends on the respective design of a processor and can vary from type to type.
Many digital processors have instructions of variable execution time. However, many designs into which such processors are incorporated, require a known interrupt latency so that processes can be controlled properly. Therefore, digital processors are sometimes designed to have a constant or fixed interrupt latency. In such digital processors having fixed latency the exception processing preamble must be long enough to accommodate the completion of the longest instruction. If it is not, the latency between the interrupt assertion and the start of the Interrupt Service Routine (ISR) will vary depending upon which instruction the central processing unit (CPU) was executing at the time of the exception, and may introduce “latency jitter.” Fixed latency solves the “latency jitter” issue but at the expense of wasted interrupt response time. In CPUs with deep instruction pipelines and/or instruction pre-fetch logic, the worse case preamble necessary to support fixed latency can become very long. This can be very restrictive for a user.
Therefore there exists a need for a more flexible processor in handling and in particular pre-processing interrupts.